Senior Memory Layout Engineer

Design and develop custom layouts for SRAM, ROM, Register Files, Sense Amplifiers, Decoders, and Control Blocks Perform floorplanning, placement, routing, and layout optimization Execute DRC, LVS, ERC, and parasitic extraction (PEX) checks Work closely with Circuit Design, Verification, and Physical Design teams Support post-layout verification and timing closure Ensure layout quality and timely project delivery Mentor junior engineers and participate in layout reviews.