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Formal Verification Engineer

Microsoft Corporation India Pvt Ltd. Verified employer

Actively hiring · Posted today · JEV2610486B9E1FE2

SalarySalary not disclosed
Experience4+ yrs
LocationBengaluru/Bangalore, Karnataka
Work modeOffice · Full time
Openings1
DepartmentResearch & Development
ShiftDay Shift
IndustryResearch & Development

Job description

Formal Verification Engineer II Overview We are seeking an experienced Formal Verification Engineer with 4+ years of expertise in SoC/IP verification using formal methods. The ideal candidate will drive formal verification strategy, develop scalable verification environments, create assertions and properties, perform architectural and RTL verification, and collaborate closely with architects, designers, and DV teams to ensure high-quality silicon delivery. Responsibilities Define and execute formal verification strategies for complex IPs, subsystems, and SoCs.Develop formal verification plans based on architecture and microarchitecture specifications. Create SystemVerilog Assertions (SVA), formal properties, assumptions, covers, and checkers. Debug counterexamples and work closely with designers to root-cause and resolve design issues. Drive verification closure through proof convergence, coverage analysis, and methodology improvements.Develop reusable formal verification components, libraries, and automation flows. Contribute to formal verification methodology evolution, AI-assisted verification workflows, and best practices. Mentor early career engineers and review verification plans, properties, and results. Collaborate with cross-functional teams including Architecture, RTL Design, DV, Emulation, and Silicon Validation. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 4+ years of experience in semiconductor verification with significant focus on Formal Verification. Strong understanding of Digital Design FundamentalsComputer Architecture and SoC DesignExpertise in SystemVerilog and SystemVerilog Assertions (SVA). Hands-on experience with formal verification tools such as:Cadence JasperGoldSynopsys VC FormalStrong debugging and analytical skills. This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. Experience Level Mid Level

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