Principal Engineer – Physical Design (SoC / RTL to GDSII)

We are hiring a Principal Engineer – Physical Design to lead end-to-end implementation of advanced-node SoCs (7nm and below), from RTL to GDSII.Key Responsibilities:Lead SoC / full-chip physical design and integrationDrive floorplanning, partitioning, and P&R (APR)Define chip-level architecture for performance, power, and areaOwn clocking strategy, power planning, and dataflowHandle IO ring design, bump planning, and package co-designEnsure physical verification closure (DRC, LVS, DFM)Develop and own P&R flows and methodologiesCollaborate with cross-functional teams (architecture, RTL, packaging)Mentor junior engineers and lead executionRequirements:15+ years in VLSI Physical DesignExperience in 7nm or below technology nodesStrong expertise in floorplanning, STA, and P&RHands-on with tools like ICC2 / Innovus / PrimeTimeExperience in full-chip SoC tape-outsStrong understanding of ESD, latch-up, and foundry rulesExperience with package integration and RDL is a plus