Analog Circuit Design - Internship (WFH)

About the internship:Selected intern's day-to-day responsibilities include:

1 . Assist with transistor-level design and simulation of SerDes building blocks in Cadence Virtuoso/Spectre

2. Support characterization and verification tasks: building test benches, automating corner and Monte Carlo sweeps via OCEAN/Python scripts, post-processing simulation data and maintaining regression result databases for the high-speed interconnect IP.

3. Assist with layout-aware design and physical verification support reviewing parasitic extraction (RC/EM) results, performing post-layout re-simulation, checking matching/floor plan constraints on analog blocks, and preparing design documentation, specification sheets and data sheet content under the supervision of senior analog design engineers.Who can apply:Only those candidates can apply who:are available for the work from home job/internshipcan start the work from home job/internship between 14th Sep'26 and 19th Oct'26are available for duration of 6 monthshave relevant skills and interestsare Electronics Engineering studentsStipend:INR₹ 30,000 - 50,000 /monthDeadline:[hidden]:59:59Other perks:Certificate, Letter of recommendation, Flexible work hours, 5 days a weekSkills required:Circuit Design, Cadence, Circuit Modeling & Simulation, Simulation and Modeling and ClaudeOther Requirements:Additional candidate preferences:- Currently pursuing an MS or PhD (or final-year B.Tech/BS) in Electrical/Electronics Engineering with coursework in analog IC design, high-speed links, or RF/mixed-signal circuits.- Hands-on familiarity with Cadence Virtuoso, Spectre/APS, and ADE Explorer/Assembler; exposure to Verilog-A or Verilog-AMS modeling is a plus.- Working knowledge of SerDes fundamentals — equalization (CTLE, DFE, FFE), CDR architectures, PLL/clocking, jitter and noise analysis, and channel/S-parameter behavior.- Scripting proficiency in Python, MATLAB, OCEAN, or TCL for simulation automation and data post-processing.- Demonstrated ability to use AI tools (LLM-based assistants, AI coding and documentation tools) productively in an engineering workflow — for simulation script generation, data analysis, literature and specification review, and design documentation — including sound judgment about verifying AI-generated output against simulation results and specifications.- Prior tapeout, lab bring-up, or bench measurement experience (VNA, high-speed scope, BERT) in an academic or industry setting is preferred.- Strong analytical and problem-solving skills, attention to detail in documentation, and ability to work independently within a small, fast-moving engineering team.- Effective written and verbal communication for design reviews and technical documentation.About Company:Accelora AI is building next-generation connectivity intellectual property designed to unlock the full potential of large-scale AI infrastructure interconnect technologies that deliver higher bandwidth, lower latency, improved power efficiency, and seamless scalability for the AI era.

Responsibilities

Selected intern's day-to-day responsibilities include:

1 . Assist with transistor-level design and simulation of SerDes building blocks in Cadence Virtuoso/Spectre

2. Support characterization and verification tasks: building test benches, automating corner and Monte Carlo sweeps via OCEAN/Python scripts, post-processing simulation data and maintaining regression result databases for the high-speed interconnect IP.

3. Assist with layout-aware design and physical verification support reviewing parasitic extraction (RC/EM) results, performing post-layout re-simulation, checking matching/floor plan constraints on analog blocks, and preparing design documentation, specification sheets and data sheet content under the supervision of senior analog design engineers.