Lead Analog IC Test Engineer Mixed-Signal & Power Management

At TI, we design and manufacture analog and embedded semiconductors that power the world's most critical applications from automotive and industrial to personal electronics and communications infrastructure. Our Analog Test Engineering team plays a pivotal role in ensuring every chip that leaves our fabs meets the highest standards of quality, reliability, and performance.

About the Role

We are looking for a Senior Analog IC Test Engineer to join our growing team focused on mixed-signal and power management ICs. In this role, you will own the full test lifecycle from test strategy development and ATE program development to silicon characterization and production test optimization. You will work closely with design, product, and reliability teams to ensure our analog ICs are production-ready, fully characterized, and built to last.

What You'll Do

Test Development

Develop, debug, and optimize ATE test programs for analog and mixed-signal ICs on platforms such as Advantest, Teradyne, or National InstrumentsWrite test plans covering DC parametrics, AC performance, functional verification, and limit settingDefine test flows for wafer sort, final test, and system-level test (SLT) Silicon Characterization

Lead bench and ATE characterization of new silicon across PVT (Process, Voltage, Temperature) cornersGenerate characterization reports and work with design teams to close performance gapsSupport first-silicon debug and root cause analysis of test escapes or anomalies Test Hardware

Design or review Device Interface Boards (DIBs), load boards, and probe cardsEnsure signal integrity and minimize parasitic effects in test hardware for high-frequency analog measurements Yield & Quality

Monitor and analyze yield trends, identify systematic failures, and drive continuous improvementCollaborate with product engineering on test time reduction (TTR) and cost-of-test optimizationSupport DPPM reduction initiatives and reliability qualification programs (HTOL, ELFR, ESD) Cross-Functional Collaboration

Partner with analog design engineers to understand circuit intent and translate it into robust test coverageEngage with manufacturing and quality teams for smooth product ramp to high-volume productionContribute to design-for-testability (DFT) reviews during the early stages of IC development

What You Bring

Education & Experience: B.S., M.S., or Ph.D. in Electrical Engineering with 5+ years of hands-on analog/mixed-signal IC test engineering experience

ATE Expertise: Proficiency in developing test programs on industry-standard ATE platforms (Advantest V93000, Teradyne UltraFLEX, or similar)

Analog Fundamentals: Strong understanding of analog parameters offset voltage, noise, PSRR, CMRR, THD, bandwidth, slew rate, and power supply rejection

Mixed-Signal Knowledge: Familiarity with ADC/DAC testing, including DNL, INL, ENOB, SFDR, and SNR measurements

Lab Skills: Hands-on experience with precision bench instruments DMMs, spectrum analyzers, oscilloscopes, LCR meters, and signal generators

Programming: Proficiency in C/C++, Python, or LabVIEW for test automation and data analysis

Statistical Analysis: Experience with Cpk, Cp, Gauge R&R, and statistical process control (SPC) for limit setting and yield analysis

Bonus Points If You Have

Experience testing power management ICs LDOs, DC-DC converters, gate drivers, or battery management systems

Familiarity with GaN or SiC power stage characterization and high-voltage test safety protocols

Exposure to automotive-grade (AEC-Q100) or high-reliability IC qualification

Knowledge of BIST (Built-In Self-Test) and DFT methodologies for analog circuits

Experience with wafer-level reliability (WLR) and failure analysis techniques

Why TI

Work on analog technology that is embedded in billions of devices worldwide Access to state-of-the-art test equipment and world-class semiconductor fabs A culture that values engineering depth and rewards technical excellence Competitive compensation, comprehensive benefits, and meaningful career growth opportunities .