Senior Analog/Mixed-Signal IC Design Engineer

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Senior Analog/Mixed-Signal IC Design Engineer

Bangalore

Company Description

We are a leading provider of high-performance, ultra-low power IP cores optimized for advanced semiconductor nodes, enabling the development of cutting-edge systems-on-chip (SoCs) for applications such as 5G, AI, LiDAR, radar, networking, and IoT. Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps.

Milpitas / Austin / Bangalore / Fort Collins / Billerica / Lisbon

Engineering Analog/Mixed-Signal Circuit Design /

Full-time /

Hybrid

Senior Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

Qualifications

5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processesThorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc.Must have a track record of successfully taking designs to productionMust have experience with evaluating silicon on bench and familiarity with standard lab equipmentStrong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysisExperience with analog and digital behavioral modeling, and/or synthesis of digital control blocksFamiliar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation toolsMATLAB understanding would be preferred but not mandatoryFamiliar with designing circuits for electromigration and ESD compliance in submicron CMOS processMust be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processesMust be able to work independently, create and adhere to schedulesMust possess strong written and verbal communication skills with an ability to work with teams spread across geographic locationsShould be able to seek help proactively as well as share and pass on knowledge

Contact:

Uday

Mulya Technologies

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"Mining The Knowledge Community" .