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Design for Testability Engineer

Corp Match Verified employer

Actively hiring · Posted 7d ago · JEV2611B30403422D

SalarySalary not disclosed
Experience3 yrs
LocationKarnataka
Work modeRemote · Full time
Openings1
IndustryCorporate IT

Job description

Job Description – DFT Engineer

Company: Corp Match Private Limited

Job Title: DFT Engineer (Design for Test)

Job Location: Bangalore, India

Employment Type: Full-Time

Experience: Freshers / Entry-Level (as per eligibility criteria)

Eligibility Criteria

B.Tech graduates from the 2024 batch or M.Tech graduates from the 2026 batch.

Specialization in VLSI, Electronics, Electrical, ECE, or related engineering disciplines.

Candidates with training in VLSI Design and DFT concepts will be preferred.

Job Summary

We are looking for motivated and technically strong DFT Engineers to work on semiconductor design and testability projects. The ideal candidate should have a basic understanding of digital electronics, VLSI design concepts, and Design for Testability methodologies.

Roles and Responsibilities

Understand Design for Testability (DFT) concepts and methodologies.

Assist in implementing DFT techniques such as scan insertion, ATPG, and boundary scan.

Support scan-chain architecture and test-pattern generation activities.

Work with RTL, synthesis, and physical design teams to ensure testability.

Assist in debugging DFT-related design issues and analyzing test coverage.

Learn and work with industry-standard EDA tools for DFT implementation and verification.

Prepare technical documentation and project reports.

Required Skills

Basic knowledge of Digital Electronics and Verilog HDL.

Understanding of VLSI design flow and semiconductor fundamentals.

Familiarity with scan chains, ATPG, fault models, and test coverage is an advantage.

Knowledge of RTL design and synthesis concepts is desirable.

Good analytical, problem-solving, and communication skills.

Willingness to learn and work on real-time semiconductor projects.

Preferred Skills

Exposure to Synopsys or Siemens EDA DFT tools.

Knowledge of scan insertion, JTAG, MBIST, and LBIST concepts.

Completion of relevant VLSI/DFT training or academic projects.

How to Apply

Interested and eligible candidates can share their updated resume with Corp Match Private Limited. [hidden]

Website: [hidden]

How to apply

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  2. Apply with one tap — your profile is shared directly with Corp Match.
  3. Track your application and get updates by email and WhatsApp.
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Design for Testability EngineerSalary not disclosed · Karnataka
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